This invention relates to the operational control of a digital computer system, and more particularly, to the digital logic circuitry for reading operand data stored in a temporary storage memory in a forward or reverse direction, wherein the operand data can be multiple varible length operands.
An objective, which almost always faces designers furthering the advancement of digital computers, is to decrease the time required for executing each of the instructions executed by the digital computer, thereby decreasing the overall time required by the digital computer to perform a predefined task and increasing the efficiency of the digital computer. Many schemes have been devised by digital computer designers in an attempt to meet this objective. In the execution of some instructions, the reading of stored operand data in a reverse direction can be helpful in speeding up the execution time of the instruction. Reverse reading of an operand (i.e., reading from least significant bit (LSB) to most significant bit (MSB) rather than a normal read of MSB to LSB) can be especially useful in arithmetic operations such as addition in which the adding operations are performed LSB to MSB. The capability to reverse read therefore allows execution to start without having to wait for the entire operand data read to be completed.
Therefore, there is provided by the logic circuit of the present invention an apparatus for reading operand data stored in a temporary storage memory (i.e., stack) in either a forward or reverse direction.